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low power, 8.5 mw, 2.3 v to 5.5 v, programmable waveform generator AD9837 rev. 0 informatio responsibi rights of th license is g trademar u.s.a. .com served. n furnished by analog devices is believed to be accurate and reliable. however, no lity is assumed by analog devices for its use, nor for any infringements of patents or other ird parties that may result from its use. specifications subject to change without notice. no ranted by implication or otherwise under any patent or patent rights of analog devices. ks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, tel: 781.329.4700 www.analog fax: 781.461.3113 ?2011 analog devices, inc. all rights re features digitally programmable frequency and phase 8.5 mw power consumption at 2.3 v mclk speed: 16 mhz (b grade), 5 mhz (a grade) 28-bit resolution: 0.06 hz at 16 mhz reference clock sinusoidal, triangular, and square wave outputs 2.3 v to 5.5 v power supply 3-wire spi interface extended temperature range: ?40c to +125c power-down option 10-lead lfcsp applications frequency stimulus/waveform generation liquid and gas flow measurement sensory applications: proximity, motion, and defect detection line loss/attenuation test and medical equipment sweep/clock generators time domain reflectometry (tdr) applications general description the AD9837 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. waveform generation is required in various types of sensing, actuation, and time domain reflectometry (tdr) applications. the output frequency and phase are software programmable, allowing easy tuning. the frequency registers are 28 bits wide: with a 16 mhz clock rate, resolution of 0.06 hz can be achieved; with a 5 mhz clock rate, the AD9837 can be tuned to 0.02 hz resolution. the AD9837 is written to via a 3-wire serial interface. this serial interface operates at clock rates up to 40 mhz and is compatible with dsp and microcontroller standards. the device operates with a power supply from 2.3 v to 5.5 v. the AD9837 has a power-down (sleep) function. sections of the device that are not being used can be powered down to minimize the current consumption of the part. for example, the dac can be powered down when a clock output is being generated. the AD9837 is available in a 10-lead lfcsp_wd package. functional block diagram serial interface and control logic sclk sdata fsync 16-bit control register 12-bit phase1 reg 12-bit phase0 reg mux sin rom 10-bit dac mux 12 on-board reference agnd dgnd vdd phase accumulator (28-bit) regulator cap/2.5v 2.5v avdd/ dvdd mux divide by 2 msb mux full-scale control AD9837 comp vout r 200 ? mclk 28-bit freq1 reg 28-bit freq0 reg 0 9070-001 figure 1. www..net
AD9837 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 4 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? test circuit ........................................................................................ 9 ? terminology .................................................................................... 10 ? theory of operation ...................................................................... 11 ? circuit description ......................................................................... 12 ? numerically controlled oscillator plus phase modulator ... 12 ? sin rom ..................................................................................... 12 ? digital-to-analog converter (dac) ....................................... 12 ? regulator ...................................................................................... 12 ? functional description .................................................................. 13 ? serial interface ............................................................................ 13 ? latency period ............................................................................ 13 ? control register ......................................................................... 13 ? frequency and phase registers ................................................ 15 ? reset function ............................................................................ 16 ? sleep function ............................................................................ 16 ? vout pin ................................................................................... 16 ? powering up the AD9837 ......................................................... 16 ? applications information .............................................................. 19 ? grounding and layout .............................................................. 19 ? interfacing to microprocessors................................................. 19 ? evaluation board ............................................................................ 21 ? system demonstration platform .............................................. 21 ? AD9837 to sport interface ..................................................... 21 ? evaluation kit ............................................................................. 21 ? crystal oscillator vs. external clock ....................................... 21 ? power supply ............................................................................... 21 ? evaluation board schematics ................................................... 22 ? evaluation board layout ........................................................... 24 ? outline dimensions ....................................................................... 25 ? ordering guide .......................................................................... 25 ? revision history 4/11revision 0: initial version
AD9837 rev. 0 | page 3 of 28 specifications vdd = 2.3 v to 5.5 v, agnd = dgnd = 0 v, t a = t min to t max , unless otherwise noted. table 1. parameter 1 min typ max unit test conditions/comments signal dac specifications resolution 10 bits update rate a grade 5 msps b grade 16 msps v out maximum 0.645 v v out minimum 37 mv v p-p 0.610 v v out tc 200 ppm/c dc accuracy integral nonlinearity (inl) 1.0 lsb differential nonlinearity (dnl) 0.5 lsb dds specifications dynamic specifications signal-to-noise ratio (snr) a grade ?64 db f mclk = 5 mhz, f out = f mclk /4096 b grade ?64 db f mclk = 16 mhz, f out = f mclk /4096 total harmonic distortion (thd) a grade ?68 dbc f mclk = 5 mhz, f out = f mclk /4096 b grade ?68 dbc f mclk = 16 mhz, f out = f mclk /4096 spurious-free dynamic range (sfdr) wideband (0 to nyquist) a grade ?65 dbc f mclk = 5 mhz, f out = f mclk /50 b grade ?65 dbc f mclk = 16 mhz, f out = f mclk /50 narrow-band (200 khz) a grade ?94 dbc f mclk = 5 mhz, f out = f mclk /50 b grade ?97 dbc f mclk = 16 mhz, f out = f mclk /50 clock feedthrough ?67 dbc wake-up time 1 ms logic inputs input high voltage, v inh 1.7 v 2.3 v to 2.7 v power supply 2.0 v 2.7 v to 3.6 v power supply 2.8 v 4.5 v to 5.5 v power supply input low voltage, v inl 0.5 v 2.3 v to 2.7 v power supply 0.7 v 2.7 v to 3.6 v power supply 0.8 v 4.5 v to 5.5 v power supply input current, i inh /i inl 10 ma input capacitance, c in 3 pf power supplies f mclk = 16 mhz, f out = f mclk /4096 vdd 2.3 5.5 v i dd a grade 3.7 5.0 ma i dd code dependent; see figure 6 b grade 4.5 5.5 ma i dd code dependent; see figure 7 low power sleep mode 0.5 0.8 ma dac powered down (sleep1 and sleep12 bits = 11; see table 15 ) 1 operating temperature range is ?40c to +125c; typical specifications are at 25c.
AD9837 rev. 0 | page 4 of 28 timing characteristics vdd = 2.3 v to 5.5 v, agnd = dgnd = 0 v, unless otherwise noted. table 2. parameter 1 limit at t min to t max unit description t 1 62.5 ns min mclk period (f mclk = 16 mhz) t 2 25 ns min mclk high duration (f mclk = 16 mhz) t 3 25 ns min mclk low duration (f mclk = 16 mhz) t 4 25 ns min sclk period t 5 10 ns min sclk high duration t 6 10 ns min sclk low duration t 7 5 ns min fsync to sclk falling edge setup time t 8 10 ns min sclk falling edge to fsync rising edge time t 4 ? 5 ns max t 9 5 ns min data setup time t 10 3 ns min data hold time t 11 5 ns min sclk high to fsync falling edge setup time 1 guaranteed by design; not production tested. timing diagrams t 2 t 1 mclk t 3 0 9070-00 3 figure 2. master clock t 5 t 4 t 6 t 7 t 8 t 10 t 9 41d51d d0 d1 d2 d14 sclk fsync sdata d15 t 11 09070-004 figure 3. serial timing
AD9837 rev. 0 | page 5 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating vdd to agnd ?0.3 v to +6 v vdd to dgnd ?0.3 v to +6 v agnd to dgnd ?0.3 v to +0.3 v cap/2.5v 2.75 v digital i/o voltage to dgnd ?0.3 v to vdd + 0.3 v analog i/o voltage to agnd ?0.3 v to vdd + 0.3 v operating temperature range industrial (b version) ?40c to +125c storage temperature range ?65c to +150c maximum junction temperature 150c lead temperature, soldering (10 sec) 300c ir reflow, peak temperature 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jc unit 10-lead lfcsp_wd (cp-10-9) 206 44 c/w esd caution
AD9837 rev. 0 | page 6 of 28 pin configuration and fu nction descriptions comp 1 vdd 2 cap/2.5v 3 dgnd 4 mclk 5 vout 10 agnd 9 fsync 8 sclk 7 sdata 6 AD9837 top view (not to scale) 09070-005 notes 1. connect exposed pad to ground. figure 4. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 comp dac bias pin. this pin is used for decoupling the dac bias voltage. 2 vdd positive power supply for the analog and digital inte rface sections. the on-board 2.5 v regulator is also supplied from vdd. vdd can have a value from 2.3 v to 5.5 v. a 0.1 f and a 10 f decoupling capacitor should be connected between vdd and agnd. 3 cap/2.5v the digital circuitry operates from a 2.5 v power supply. this 2.5 v is generated from vdd using an on-board regulator when vdd exceeds 2.7 v. the regulator requires a decoupling capacitor of 100 nf typical, which is connected from cap/2.5v to dgnd. if vdd is less than or equal to 2.7 v, cap/2.5v should be tied directly to vdd to bypass the on-board regulator. 4 dgnd digital ground. 5 mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. the output frequency accuracy and phase no ise are determined by this clock. 6 sdata serial data input. the 16-bit seri al data-word is appl ied to this input. 7 sclk serial clock input. data is clocked into the AD9837 on each falling edge of sclk. 8 fsync active low control input. fsync is the frame synchroniz ation signal for the input data. when fsync is taken low, the internal logic is informed that a new word is being loaded into the device. 9 agnd analog ground. 10 vout voltage output. the analog and digital output from the AD9837 is available at this pin. an external load resistor is not required because the device has a 200 resistor on board. ep exposed pad. connect the exposed pad to ground.
AD9837 rev. 0 | page 7 of 2 0 2 4 6 8 1012141618 mclk frequency (mhz) 09070-00 typical performance characteristics 5.0 3.0 i dd (ma) 6 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 vdd = 5v vdd = 3v figure 5. typical current consumption (i dd ) vs. mclk frequency for f out = mclk/10 4.5 4.4 4.3 4.2 4.1 4.0 3.9 3.8 i dd (ma) ? 98 ?104 ?103 ?102 ?101 ?100 ?99 02468 18 16 141210 sfdr (db) mclk frequency (mhz) 09070-009 figure 8. narrow-band sfdr vs. mclk frequency, f out = mclk/50 to 200 khz ? 50 ?55 ?60 ?65 ?70 1 3 5 7 9 11 13 15 sfdr (db) mclk frequency (mhz) 09070-010 1 10 100 1000 output frequency (khz) 09070-007 vdd = 3v vdd = 5v figure 6. typical i dd vs. output frequency for f mclk = 5 mhz 4.9 4.4 4.8 4.7 4.6 4.5 4.3 4.2 4.1 4.0 i dd (ma) mclk/7 mclk/50 ?56 ?70 0 2 4 6 8 1012141618 snr (db) mclk frequency (mhz) 09070-011 ?68 ?66 ?64 ?62 ?60 ?58 figure 9. wideband sfdr vs. mclk frequency figure 10. snr vs. mclk frequency 1 10 100 1k 10k output frequency (khz) 09070-008 vdd = 3v vdd = 5v figure 7. typical i dd vs. output frequency for f mclk = 16 mhz 8
AD9837 rev. 0 | page 8 of 2 400 ?40 ?20 0 20 40 60 80 140120100 temperature (c) 09070-012 8 1000 900 800 700 600 500 wake-up time (s) vdd = 2.3v vdd = 5.5v figure 11. wake-up time vs. temperature 1.180 1.168 1.170 1.172 1.174 1.176 1.178 v ref (v) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 10090 10 20 30 40 50 60 70 80 power (db) frequency (khz) 09070-015 figure 14. power vs. frequency, f mclk = 16 mhz, f out = 7.692 khz, frequency word = 0x1f81a 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 02 . 5 0.5 1.0 1.5 2.0 power (db) frequency (mhz) 09070-016 figure 15. power vs. frequency, f mclk = 5 mhz, f out = 0.714285 mhz = f mclk /7, frequency word = 0x2492492 1.164 1.166 ?40 ?20 0 20 40 60 80 100 140120 temperature (c) 09070-013 vdd = 2.7v vdd = 5.0v figure 12. v ref vs. temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 power (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 power (db) 7 04 123 frequency (mhz) 09070-01 figure 16. power vs. frequency, f mclk = 16 mhz, f out = 2.285714 mhz = f mclk /7, frequency word = 0x2492492 ?90 ?100 0 10090 10 20 30 40 50 60 70 80 frequency (khz) 09070-014 figure 13. power vs. frequency, f mclk = 5 mhz, f out = 2.4 khz, frequency word = 0x1f751
AD9837 rev. 0 | page 9 of 28 test circuit vout comp 12 AD9837 10-bit dac sin rom 20pf 10nf vdd regulator 100nf cap/2.5v 09070-002 figure 17. test circuit used to test specifications
AD9837 rev. 0 | page 10 of 28 terminology integral nonlinearity (inl) total harmonic distortion (thd) inl is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale, a point 0.5 lsb below the first code transition (000 00 to 000 01), and full scale, a point 0.5 lsb above the last code transition (111 10 to 111 11). the error is expressed in lsbs. total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the AD9837, thd is defined as 1 2 6 2 5 2 4 2 3 2 2 log20 v vvvvv thd ++++ = differential nonlinearity (dnl) where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. dnl is the difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. a specified dnl of 1 lsb maximum ensures monotonicity. output compliance signal-to-noise ratio (snr) output compliance refers to the maximum voltage that can be generated at the output of the dac to meet the specifications. when voltages greater than that specified for the output compli- ance are generated, the AD9837 may not meet the specifications listed in the data sheet. snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency. the value for snr is expressed in decibels. clock feedthrough there is feedthrough from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the output spectrum of the AD9837. spurious-free dynamic range (sfdr) along with the frequency of interest, harmonics of the funda- mental frequency and images of these frequencies are present at the output of a dds device. the spurious-free dynamic range (sfdr) refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the 0 to nyquist bandwidth. the narrow-band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz about the fundamental frequency.
AD9837 rev. 0 | page 11 of 28 theory of operation sine waves are typically thought of in terms of their magnitude form: a(t) = sin(t). however, sine waves are nonlinear and not easy to generate except through piecewise construction. on the other hand, the angular information is linear in nature; that is, the phase angle rotates through a fixed angle for each unit of time. the angular rate depends on the frequency of the signal by the traditional rate of = 2 f . magnitude phase + 1 0 ?1 2 28 0 2 4 6 2 4 6 0 9070-0 09070-040 23 figure 18. sine wave knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined as follows: phase = t (1) solving for , = phase/ t = 2 f (2) solving for f and substituting the reference clock frequency for the reference period (1/f mclk = t), f = phase f mclk M2 (3) the AD9837 builds the output base d on this simple equation. a simple dds chip can implement this equation with three major subcircuits: numerically controlled oscillator (nco) plus phase modulator, sin rom, and digital-to-analog converter (dac). each subcircuit is described in the circuit description section. the AD9837 provides a sampled signal with its output following the nyquist sampling theorem. specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency and the selected output frequency. a graphical representation of the sampled spectrum with aliased images is shown in figure 19 . the prominence of the aliased images depends on the ratio of f out to mclk. if the ratio is small, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized dac output. in fact, depend- ing on the f out /reference clock ratio, the first aliased image can be on the order of ?3 db below the fundamental. external filtering is required if the aliased image is within the output band of interest. system clock f out f c ? f out f c + f out 2 f c ? f out 2 f c + f out 3 f c ? f out 3 f c + f out f c 0hz first image second image third image fourth image fifth image sixth image 2 f c frequency (hz) signal amplitude sin(x)/x envelope x = ( f / f c ) 3 f c figure 19. dac output spectrum
AD9837 rev. 0 | page 12 of 28 circuit description the AD9837 is a fully integrated direct digital synthesis (dds) chip. the chip requires a reference clock and decoupling capa- citors to provide digitally created sine waves up to 8 mhz. in addition to the generation of this rf signal, the chip is fully capable of a broad range of simple and complex modulation schemes. these modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using dsp techniques. the internal circuitry of the AD9837 consists of the following main sections: a numerically controlled oscillator (nco), frequency and phase modulators, sin rom, a digital-to-analog converter, and a regulator. numerically controlled oscillator plus phase modulator the AD9837 consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. the main component of the nco is a 28-bit phase accumulator. continuous time signals have a phase range of 0 to 2. outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. the digital implementation is no different. the accumulator simply scales the range of phase numbers into a multibit digital word. the phase accumulator in the AD9837 is implemented with 28 bits. therefore, in the AD9837, 2 = 2 28 . likewise, the phase term is scaled into this range of numbers: 0 < phase < 2 28 ? 1 with these substitutions, equation 3 becomes f = phase f mclk M2 28 (4) where 0 < phase < 2 28 ? 1. the input to the phase accumulator can be selected from either the freq0 register or the freq1 register and is controlled by the fsel bit in the control register. ncos inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. following the nco, a phase offset can be added to perform phase modulation using the 12-bit phase registers. the contents of one of these phase registers is added to the msbs of the nco. the AD9837 has two phase registers; their resolution is 2/4096. sin rom to make the output from the nco useful, it must be converted from phase information into a sinusoidal value. because phase information maps directly to amplitude, the sin rom uses the digital phase information as an address to a lookup table and converts the phase information into amplitude. although the nco contains a 28-bit phase accumulator, the out- put of the nco is truncated to 12 bits. using the full resolution of the phase accumulator is impractical and unnecessary because a lookup table of 2 28 entries would be required. it is only necessary to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit dac. therefore, the sin rom must have two bits of phase resolution more than the 10-bit dac. the sin rom is enabled using the mode bit (bit d1) in the control register (see table 16 ). digital-to-analog converter (dac) the AD9837 includes a high impedance, current source, 10-bit dac. the dac receives the digital words from the sin rom and converts them into the corresponding analog voltages. the dac is configured for single-ended operation. an external load resistor is not required because the device has an on-board 200 resistor. the dac generates an output voltage of 0.6 v p-p typical. regulator vdd provides the power supply required for the analog section and the digital section of the AD9837. this supply can have a value of 2.3 v to 5.5 v. the internal digital section of the AD9837 is operated at 2.5 v. an on-board regulator steps down the voltage applied at vdd to 2.5 v. when the applied voltage at the vdd pin of the AD9837 is less than or equal to 2.7 v, the cap/2.5v and vdd pins should be tied together to bypass the on-board regulator.
AD9837 rev. 0 | page 13 of 28 functional description serial interface the AD9837 has a standard 3-wire serial interface that is compatible with the spi, qspi?, microwire?, and dsp interface standards. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this oper- ation is given in figure 3 . fsync is a level triggered input that acts as a frame synchroni- zation and chip enable input. data can be transferred into the device only when fsync is low. to start the serial data transfer, fsync should be taken low, observing the minimum fsync to sclk falling edge setup time, t 7 (see tabl e 2 ). after fsync goes low, serial data is shifted into the input shift register of the device on the falling edges of sclk for 16 clock pulses. fsync can be taken high after the 16th falling edge of sclk, observing the minimum sclk falling edge to fsync rising edge time, t 8 . alternatively, fsync can be kept low for a multiple of 16 sclk pulses and then brought high at the end of the data transfer. in this way, a continuous stream of 16-bit words can be loaded while fsync is held low; fsync goes high only after the 16th sclk falling edge of the last word loaded. the sclk can be continuous, or it can idle high or low between write operations. in either case, it must be high when fsync goes low (t 11 ). for an example of how to program the AD9837, see the an-1070 application note on the analog devices, inc., website. the AD9837 has the same register settings as the ad9833/ ad9834. latency period a latency period is associated with each asynchronous write operation in the AD9837. if a selected frequency or phase register is loaded with a new word, there is a delay of seven or eight mclk cycles before the analog output changes. the delay can be seven or eight cycles, depending on the position of the mclk rising edge when the data is loaded into the destination register. control register the AD9837 contains a 16-bit control register that allows the user to configure the operation of the AD9837. all control bits other than the mode bit are sampled on the internal falling edge of mclk. figure 20 illustrates the functions of the control bits. table 7 describes the individual bits of the control register. the different functions and the various output options of the AD9837 are described in more detail in the following sections. to inform the AD9837 that the contents of the control register will be altered, bit d15 and bit d14 must be set to 0, as shown in table 6 . table 6. control register bits d15 d14 d13 to d0 0 0 control bits sin rom phase accumulator (28-bit) sleep12 sleep1 reset mode + opbiten div2 opbiten (low power) 10-bit dac 0 mux 1 vout 1 mux 0 digital output (enable) divide by 2 d15 0 d14 0 d13 b28 d12 hlb d11 fsel d10 psel d9 0 d8 reset d7 sleep1 d6 sleep12 d5 opbiten d4 0 d3 div2 d2 0 d1 mode d0 0 09070-024 figure 20. function of control bits
AD9837 rev. 0 | page 14 of 28 table 7. control register bit descriptions bit bit name description d13 b28 two write operations are required to load a complete word into either of the frequency registers. b28 = 1 allows a complete word to be loaded into a freq uency register in two consecutive writes. the first write contains the 14 lsbs of the frequency word, and the second write contains the 14 msbs. the first two bits of each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both consecutive writes. see table 9 for the appropriate addresses. the write to the frequency register occurs after both words have been loaded, so the register never holds an intermediate value. an example of a complete 28-bit write is shown in table 10 . note, however, that consecutive 28-bit writes to the same frequency register are not allowed; to execute consecutive 28-bit writes, you must alternate between the frequency registers. b28 = 0 configures the 28-bit frequency register to operate as two 14-bit registers, one containing the 14 msbs and the other containing the 14 lsbs. in this way, the 14 msbs of the frequency word can be altered independently of the 14 lsbs, and vice versa. to alter the 14 msbs or the 14 lsbs, a single write is made to the appropriate frequency address. bit d12 (hlb) informs the AD9837 whether the bi ts to be altered are the 14 msbs or the 14 lsbs. d12 hlb this control bit allows the user to co ntinuously load the msbs or lsbs of a frequency register while ignoring the remaining 14 bits. this is useful if the complete 28-bit reso lution is not required. the hlb bit is used in conjunction with the b28 bit (bit d13). the hlb bit indicates whether th e 14 bits to be loaded are transferred to the 14 msbs or the 14 lsbs of the addressed frequency register. bit d13 (b28) must be set to 0 to change the msbs or lsbs of a frequency word separately. when bit d13 (b28) is set to 1, the hlb bit is ignored. hlb = 1 allows a write to the 14 msbs of the addressed frequency register. hlb = 0 allows a write to the 14 lsbs of the addressed frequency register. d11 fsel the fsel bit defines whether the freq0 register or the freq1 register is used in the phase accumulator (see table 8 ). d10 psel the psel bit defines whether the phase0 register data or the phase1 register data is added to the output of the phase accumulator (see table 8 ). d9 reserved this bit should be set to 0. d8 reset this bit controls the reset function. reset = 1 resets internal registers to 0, which corresponds to an analog output of midscale. reset = 0 disables the reset function (see the reset function section). d7 sleep1 this bit enables or disables the internal mclk. sleep1 = 1 disables the internal mclk. the dac output remains at its present value because the nco is no longer accumulating. sleep1 = 0 enables the internal mclk (see the sleep function section). d6 sleep12 this bit powers down the on-chip dac. sleep12 = 1 powers down the on-chip dac. this is useful when the AD9837 is us ed to output the msb of the dac data. sleep12 = 0 implies that the dac is active (see the sleep function section). d5 opbiten this bit, in association with the mode bit (bit d1), controls the output at the vout pin (see table 16 ). opbiten = 1 causes the output of the dac to no longer be av ailable at the vout pin. instead, the msb (or msb/2) of the dac data is connected to the vout pin. this output is useful as a coarse clock source. the div2 bit (bit d3) controls whether the vout pin outputs the msb or the msb/2. opbiten = 0 connects the output of the dac to vout. the mode bit (bit d1) determin es whether the output is sinusoidal or triangular. d4 reserved this bit must be set to 0. d3 div2 div2 is used in association with bit d5 (opbiten). see table 16 . div2 = 1 causes the msb of the dac da ta to be output at the vout pin. div2 = 0 causes the msb/2 of the dac data to be output at the vout pin. d2 reserved this bit must be set to 0. d1 mode this bit, in association with the opbi ten bit (bit d5), controls the output at the vout pin when the on-chip dac is connected to vout. this bit should be set to 0 if the opbiten bit is set to 1 (see table 16 ). mode = 1 bypasses the sin rom, resulting in a triangle output from the dac. mode = 0 uses the sin rom to convert the phase informatio n into amplitude information, resulting in a sinusoidal signal at the output. (the opbiten bit (bit d5) must also be set to 0 for sinusoidal output.) d0 reserved this bit must be set to 0.
AD9837 rev. 0 | page 15 of 28 frequency and phase registers the AD9837 contains two frequency registers and two phase registers, which are described in table 8 . table 8. frequency and phase registers register size description freq0 28 bits frequency register 0. when the fsel bit = 0, the freq0 register defines the output frequency as a fraction of the mclk frequency. freq1 28 bits frequency register 1. when the fsel bit = 1, the freq1 register defines the output frequency as a fraction of the mclk frequency. phase0 12 bits phase offset register 0. when the psel bit = 0, the contents of the phase0 register are added to the output of the phase accumulator. phase1 12 bits phase offset register 1. when the psel bit = 1, the contents of the phase1 register are added to the output of the phase accumulator. the analog output from the AD9837 is f mclk /2 28 freqreg where freqreg is the value loaded into the selected frequency register. this signal is phase shifted by 2/4096 phasereg where phasereg is the value contained in the selected phase register. the relationship of the selected output frequency and the refer- ence clock frequency must be considered to avoid unwanted output anomalies. the flowchart in figure 24 shows the routine for writing to the frequency and phase registers of the AD9837. writing to a frequency register when writing to a frequency register, bit d15 and bit d14 of the control register give the address of the frequency register (see table 9 ). table 9. frequency register bits d15 d14 d13 to d0 0 1 14 freq0 register bits 1 0 14 freq1 register bits to change the entire contents of a frequency register, two consec- utive writes to the same address must be performed because the frequency registers are 28 bits wide. the first write contains the 14 lsbs, and the second write contains the 14 msbs. for this mode of operation, the b28 control bit (bit d13) must be set to 1. an example of a 28-bit write is shown in table 10 . table 10. writing 0xfffc000 to the freq0 register sdata input result of input word 0010 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 1, hlb (d12) = x 0100 0000 0000 0000 freq0 register write (d15, d14 = 01), 14 lsbs = 0x0000 0111 1111 1111 1111 freq0 register write (d15, d14 = 01), 14 msbs = 0x3fff note, however, that continuous writes to the same frequency register may result in intermediate updates during the writes. if a frequency sweep, or something similar, is required, it is recom- mended that users alternate between the two frequency registers. in some applications, the user does not need to alter all 28 bits of the frequency register. with coarse tuning, only the 14 msbs are altered; with fine tuning, only the 14 lsbs are altered. by setting the b28 control bit (bit d13) to 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 msbs and the other containing the 14 lsbs. in this way, the 14 msbs of the frequency word can be altered independently of the 14 lsbs, and vice versa. the hlb bit (bit d12) in the control register identifies which 14 bits are being altered (see table 11 and table 12 ). table 11. writing 0x3fff to the 14 lsbs of the freq1 register sdata input result of input word 0000 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 0, hlb (d12) = 0, that is, lsbs 1011 1111 1111 1111 freq1 register write (d15, d14 = 10), 14 lsbs = 0x3fff table 12. writing 0x00ff to the 14 msbs of the freq0 register sdata input result of input word 0001 0000 0000 0000 control word write (d15, d14 = 00), b28 (d13) = 0, hlb (d12) = 1, that is, msbs 0100 0000 1111 1111 freq0 register write (d15, d14 = 01), 14 msbs = 0x00ff writing to a phase register when writing to a phase register, bit d15 and bit d14 are set to 11. bit d13 identifies the phase register that is being loaded. table 13. phase register bits d15 d14 d13 d12 d11 to d0 1 1 0 x 12 phase0 register bits 1 1 1 x 12 phase1 register bits
AD9837 rev. 0 | page 16 of 28 the opbiten and mode bits (bit d5 and bit d1 in the control register) are used to determine the output that is available from the AD9837 (see table 16 ). reset function the reset function resets the appropriate internal registers to 0 to provide an analog output of midscale. a reset does not reset the phase, frequency, or control registers. when the AD9837 is powered up, the part should be reset (see the powering up the AD9837 section). to reset the AD9837, set the reset bit to 1. to take the part out of reset, set the bit to 0. a signal appears at the dac output seven or eight mclk cycles after the reset bit is set to 0. table 16. outputs from the vout pin opbiten bit mode bit div2 bit vout pin output 0 0 x sinusoid 0 1 x triangle 1 0 0 dac data msb/2 1 0 1 dac data msb 1 1 x reserved table 14. applying the reset function reset bit result 0 no reset applied 1 internal registers reset msb of the dac data the msb of the dac data can be output from the AD9837. by setting the opbiten bit (bit d5) to 1, the msb of the dac data is available at the vout pin. this is useful as a coarse clock source. this square wave can also be divided by 2 before being output. the div2 bit (bit d3) in the control register controls the frequency of this output from the vout pin. sleep function sections of the AD9837 that are not in use can be powered down to minimize power consumption by using the sleep function. the parts of the chip that can be powered down are the internal clock and the dac. the bits required for the sleep function are shown in tabl e 15 . sinusoidal output the sin rom converts the phase information from the frequency and phase registers into amplitude information, resulting in a sinusoidal signal at the output. to obtain a sinusoidal output from the vout pin, set the mode bit (bit d1) to 0 and the opbiten bit (bit d5) to 0. table 15. applying the sleep function sleep1 bit sleep12 bit result 0 0 no power-down 0 1 dac powered down 1 0 internal clock disabled 1 1 dac powered down and internal clock disabled triangle output the sin rom can be bypassed so that the truncated digital output from the nco is sent to the dac. in this case, the output is no longer sinusoidal. the dac produces a 10-bit linear triangular function (see figure 21 ). to obtain a triangle output from the vout pin, set the mode bit (bit d1) to 1 and the opbiten bit (bit d5) to 0. dac powered down when the AD9837 is used to output the msb of the dac data only, the dac is not required. the dac can be powered down using the sleep12 bit to reduce power consumption. v internal clock disabled when the internal clock of the AD9837 is disabled, the dac output remains at its present value because the nco is no longer accumulating. new frequency, phase, and control words can be written to the part when the sleep1 control bit is active. because the synchronizing clock (fsync) remains active, the selected frequency and phase registers can also be changed using the control bits. setting the sleep1 bit to 0 enables the mclk. any changes made to the registers while sleep1 was active are observed at the output after a latency period (see the latency period section). vout pin the AD9837 offers a variety of outputs from the chip, all of which are available from the vout pin. the available outputs are the msb of the dac data, a sinusoidal output, or a triangle output. v out min out max 2 4 6 9070-025 0 figure 21. triangle output powering up the AD9837 the flowchart in figure 22 shows the operating routine for the AD9837. when the AD9837 is powered up, the part should be reset. this resets the appropriate internal registers to 0 to provide an analog output of midscale. to avoid spurious dac outputs during AD9837 initialization, the reset bit should be set to 1 until the part is ready to begin generating an output. a reset does not reset the phase, frequency, or control registers. these registers will contain invalid data and, therefore, should be set to known values by the user. the reset bit should then be set to 0 to begin generating an output. the data appears on the dac output seven or eight mclk cycles after the reset bit is set to 0.
AD9837 rev. 0 | page 17 of 28 data write (see figure 24) select data sources wait 7/8 mclk cycles change phase? change frequency? change dac output from sin to triangle? change output to a digital signal? change phase register? change frequency register? control register write (see table 7) initialization (see figure 23) no no no no yes no yes yes no yes yes yes yes yes 09070-026 change fsel bit? change psel bit? figure 22. flowchart for AD9837 initialization and operation initialization apply reset (control register write) reset = 1 write to frequency and phase registers freq0 reg = f out0 / f mclk 2 28 freq1 reg = f out1 / f mclk 2 28 phase0 and phase1 reg = (phaseshift 2 12 )/2 (see figure 24) set reset = 0 select frequency registers select phase registers (control register write) reset bit = 0 fsel = selected frequency register psel = selected phase register 09070-027 figure 23. flowchart for initialization
AD9837 rev. 0 | page 18 of 28 no write 14 msbs or lsbs to a frequency register? (control register write) b28 (d13) = 0 hlb (d12) = 0/1 write a 16-bit word (see table 11 and table 12 for examples) write 14 msbs or lsbs to a frequency register? write to phase register? (16-bit write) d15, d14 = 11 d13 = 0/1 (choose the phase register) d12 = x d11 ... d0 = phase data write to another phase register? yes write another full 28-bit word to a frequency register? write two consecutive 16-bit words (see table 10 for example) (control register write) b28 (d13) = 1 write a full 28-bit word to a frequency register? data write yes no yes no yes on on yes yes 09070-028 figure 24. flowchart for data writes
AD9837 rev. 0 | page 19 of 28 applications information the various output options available from the AD9837 make the part suitable for a wide variety of applications, including modulation applications. the AD9837 can be used to perform simple modulation, such as frequency shift keying (fsk). more complex modulation schemes, such as gaussian minimum shift keying (gmsk) and quadrature phase shift keying (qpsk), can also be implemented using the AD9837. in an fsk application, the two frequency registers of the AD9837 are loaded with different values. one frequency represents the space frequency, and the other represents the mark frequency. using the fsel bit in the control register of the AD9837, the user can modulate the carrier frequency between the two values. the AD9837 has two phase registers, enabling the part to per- form phase shift keying (psk). with psk, the carrier frequency is phase shifted, that is, the phase is altered by an amount that is related to the bit stream input to the modulator. the AD9837 is also suitable for signal generator applications. because the msb of the dac data is available at the vout pin, the device can be used to generate a square wave. with its low current consumption, the part is also suitable for applications in which it can be used as a local oscillator. grounding and layout the printed circuit board that houses the AD9837 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes because it provides the best shielding. digital and analog ground planes should be joined in one place only. if the AD9837 is the only device that requires an agnd to dgnd connection, the ground planes should be connected at the agnd and dgnd pins of the AD9837. if the AD9837 is in a system where multiple devices require agnd to dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9837. avoid running digital lines under the device; these lines couple noise onto the die. the analog ground plane should be allowed to run under the AD9837 to avoid noise coupling. the power supply lines to the AD9837 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. a micro- strip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes and signals are placed on the other side. good decoupling is important. the AD9837 should have supply bypassing of 0.1 f ceramic capacitors in parallel with 10 f tantalum capacitors. to achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. interfacing to microprocessors the AD9837 has a standard serial interface that allows the part to interface directly with several microprocessors. the device uses an external serial clock to write the data or control information into the device. the serial clock can have a frequency of 40 mhz maximum. the serial clock can be continuous, or it can idle high or low between write operations. when data or control informa- tion is written to the AD9837, fsync is taken low and is held low until the 16 bits of data are written into the AD9837. the fsync signal frames the 16 bits of information that are loaded into the AD9837. AD9837 to 68hc11/68l11 interface figure 25 shows the serial interface between the AD9837 and the 68hc11/68l11 microcontroller. the microcontroller is con- figured as the master by setting the mstr bit in the spcr to 1. this setting provides a serial clock on sck; the mosi output drives the serial data line, sdata. because the microcontroller does not have a dedicated frame sync pin, the fsync signal is derived from a port line (pc7). the setup conditions for correct operation of the interface are as follows: ? sck idles high between write operations (cpol = 0) ? data is valid on the sck falling edge (cpha = 1) when data is to be transmitted to the AD9837, the fsync line (pc7) is taken low. serial data from the 68hc11/68l11 is trans- mitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data into the AD9837, pc7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the AD9837. only after the second eight bits are transferred should fsync be taken high again. AD9837 fsync sdata sclk 68hc11/68l11 pc7 mosi sck 09070-030 figure 25. 68hc11/68l11 to AD9837 interface
AD9837 rev. 0 | page 20 of 28 AD9837 to 80c51/80l51 interface figure 26 shows the serial interface between the AD9837 and the 80c51/80l51 microcontroller. the microcontroller is oper- ated in mode 0 so that txd of the 80c51/80l51 drives sclk of the AD9837, and rxd drives the serial data line, sdata. the fsync signal is derived from a bit programmable pin on the port (p3.3 is shown in figure 26 ). when data is to be transmitted to the AD9837, p3.3 is taken low. the 80c51/80l51 transmits data in 8-bit bytes with only eight falling sclk edges occurring in each cycle. to load the remain- ing eight bits to the AD9837, p3.3 is held low after the first eight bits are transmitted, and a second write operation is initiated to transmit the second byte of data. p3.3 is taken high following the completion of the second write operation. sclk should idle high between the two write operations. the 80c51/80l51 outputs the serial data in a format that has the lsb first. the AD9837 accepts the msb first (the four msbs are the control information, the next four bits are the address, and the eight lsbs contain the data when writing to a destination register). therefore, the transmit routine of the 80c51/80l51 must take this into account and rearrange the bits so that the msb is output first. AD9837 fsync sdata sclk 80c51/80l51 p3.3 rxd txd 09070-031 figure 26. 80c51/80l51 to AD9837 interface AD9837 to dsp56002 interface figure 27 shows the interface between the AD9837 and the dsp56002. the dsp56002 is configured for normal mode asyn- chronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated internally (sc2 = 1), the transfers are 16 bits wide (wl1 = 1, wl0 = 0), and the frame sync signal frames the 16 bits (fsl = 0). the frame sync signal is available on the sc2 pin, but it must be inverted before it is applied to the AD9837. the interface to the dsp56000/dsp56001 is similar to that of the dsp56002. dsp56002 sc2 std sck AD9837 fsync sdata sclk 9070-032 0 figure 27. dsp56002 to AD9837 interface
AD9837 rev. 0 | page 21 of 28 evaluation board the AD9837 evaluation board allows designers to evaluate the high performance AD9837 dds modulator with a minimum of effort. system demonstration platform the system demonstration platform (sdp) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. the sdp board is based on the blackfin? adsp-bf527 processor with usb connectivity to the pc through a usb 2.0 high speed port. for more information, see the sdp board product page. note that the sdp board is sold separately from the AD9837 evaluation board. AD9837 to sport interface the analog devices sdp board has a sport serial port that is used to control the serial inputs to the AD9837. the connections are shown in figure 28 . AD9837 fsync sclk sdata adsp-bf527 sport_tfs sport_tsclk sport_dt0 09070-033 figure 28. sdp to AD9837 interface evaluation kit the dds evaluation kit includes a populated, tested AD9837 printed circuit board (pcb). the schematics of the evaluation board are shown in figure 30 and figure 31 . the software provided in the evaluation kit allows the user to easily program the AD9837 (see figure 29 ). the evaluation soft- ware runs on any ibm-compatible pc with microsoft? windows? software installed (including windows 7). the software is com- patible with both 32-bit and 64-bit operating systems. more information about the evaluation software is available on the software cd and on the AD9837 product page . 09070-037 figure 29. AD9837 evaluation software interface crystal oscillator vs. external clock the AD9837 can operate with master clocks up to 16 mhz. a 16 mhz oscillator is included on the evaluation board. this oscillator can be removed and, if required, an external cmos clock can be connected to the part. options for the general oscillator include the following: ? ael 301-series oscillators, ael crystals ? sg-310scn oscillators, epson electronics power supply power to the AD9837 evaluation board can be provided from the usb connector or externally through pin connections. the power leads should be twisted to reduce ground loops.
AD9837 rev. 0 | page 22 of 28 evaluation board schematics 09070-034 figure 30. evaluation board schematic
AD9837 rev. 0 | page 23 of 28 09070-038 figure 31. sdp connector schematic
AD9837 rev. 0 | page 24 of 28 evaluation board layout 0 9070-039 figure 32. evaluation board layout
AD9837 rev. 0 | page 25 of 28 2.48 2.38 2.23 0.50 0.40 0.30 121009-a outline dimensions top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 33. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1 , 2 temperature range max mclk package description package option branding AD9837bcpz-rl ?40c to +125c 16 mhz 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 dgh AD9837bcpz-rl7 ?40c to +125c 16 mhz 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 dgh AD9837acpz-rl ?40c to +125c 5 mhz 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 dgg AD9837acpz-rl7 ?40c to +125c 5 mhz 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 dgg eval-AD9837sdz evaluation board 1 z = rohs compliant part. 2 the evaluation board fo r the AD9837 requires the system de monstration platform (sdp) board, which is sold separately.
AD9837 rev. 0 | page 26 of 28 notes
AD9837 rev. 0 | page 27 of 28 notes
AD9837 rev. 0 | page 28 of 28 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09070-0-4/11(0)

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